The present invention relates to semiconductor devices and methods of forming the same, and more particularly, to dynamic random access memory (DRAM) devices and methods of forming the same.
DRAM devices are generally able to be implemented with a high integration density as compared with static random access memory (SRAM) devices. As such, they are widely used for various products that need high capacity memory devices. A unit cell of a DRAM device generally includes a field effect transistor (hereinafter, referred to as a transistor), which is a switching device, and a capacitor for storing data. Due to ever increasing integration density of semiconductor devices, dimensions of DRAM cells are generally decreasing while a height thereof (relative to an underlying integrated circuit substrate on which the DRAM cell is formed) is increasing. Therefore, pads are typically used to provide electrical connections between relatively high position structures (e.g., a bit line and/or a capacitor) and relatively low position structures (e.g., a source/drain region of a transistor). The pads are typically disposed between the bit line or the capacitor and the source/drain region. Accordingly, an interval between the bit line or the capacitor and the source/drain region may be reduced, thereby decreasing an aspect ratio of a contact hole formed between the capacitor or the bit line and the source/drain. A conventional DRAM device will now be described further with reference to the accompanying drawings.
FIG. 1 is a plan view of a conventional DRAM device. Referring to FIG. 1, active regions 1 are two-dimensionally defined in an integrated circuit (e.g., semiconductor) substrate. The active regions 1 forming a pair of adjacent columns (corresponding to a direction from top to bottom in FIG. 1) are arranged in a zigzag pattern in order to minimize interference between structures formed thereon. A pair of gate lines 2 cross one active region 1 in parallel. The pair of gate lines 2 extend in the column direction and cross a plurality of active regions 1 forming one column.
A plurality of first pads 3 and a plurality of second pads 4 are disposed on the semiconductor substrate. The first pads 3 are connected to end portions of the active regions 1 at one side of the gate line 2 and the second pads 4 are connected to the active regions 1 between the pair of gate lines 2. A capacitor (not shown) is electrically connected to the first pads 3 and a bit line (not shown) is electrically connected to the second pads 4.
The first pads 3 form a first column and the second pads 4 form a second column. The first pads 3 of the first column respectively correspond to the active regions 1 forming the pair of columns and the second pads 4 of the second column respectively correspond to the active regions 1 forming the one column. In other words, a column of first pads 3 includes alternating pads contacting active regions 1 in adjacent columns. Therefore, the first pads 3 of the first column are arranged more closely to each other than the second pads 4 of the second column.
Because the first pads 3 of the first column are relatively closely disposed in the above-described DRAM device, an interval between the pair of adjacent first pads 3 may be the smallest of intervals that the first and second pads 3 and 4 form. Therefore, a conductive bridge may be generated between the first pads 3. That is, photoresist residues may remain between photoresist patterns for defining the first pads 3 due to narrow intervals, thereby generating the bridge therebetween during a photolithography process for defining the first and second pads 3 and 4. As semiconductor devices become more highly integrated, it generally becomes more difficult to form the first pads 3 closely and definitely without a bridge forming therebetween.